I threw together a quick demo to prove to myself that my FPGA was powered and working. It was important that the demonstration used some form of sequential logic, so that I could be sure the clock was alive and running as well.
The ideal quick and easy first project would be to just output the clock signal into a pin and drive an LED. Unfortunately, my eyeballs can’t register a 24MHz signal and I didn’t want to waste time messing around with an LED. (It’s important to ensure we don’t over draw current from the FPGA’s logic pins, so directly driving an LED, even with a current limiting resistor, is not a great idea).
I ended up with the slightly less exciting compromise of using a counter to divide the clock down to ~1Hz, and a multimeter to display that the logic level is changing. Exciting? Not so much, but suitable for a nice “Hello World” program. Besides, I picked up a Serial Enabled LCD display for the next demo, and then I’ll be able to actually display “Hello World”, that should be slightly more flashy 🙂
And now for the demo… Watch the multimeter switch from a High Logic Level (~3.3V), to a low logic level (~0V):
Here is a look at the Verilog HDL source code driving this demo:
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//Generate a very slow clock from the 24MHz input clock module SlowClock(clock_in,clock_out); //Input Ports input clock_in; //Output Ports output clock_out; //Port Definitions wire clock_out; reg [26:0] counter; //Clock Divider //Set the output pin to the MSb of the counter. assign clock_out = counter; //Essentially the counter counts up to 2^27, // then clock_out flips polarity always @ (posedge clock_in) begin counter <= counter + 1; end endmodule // End of Module counter
There is a lot more details on how to go about setting up the code, getting it compiled, assigning the pins and finally programing the FPGA. Upcoming blog posts will cover all those juicy details. Also, I’ll put together the full Bill of Materials (BOM) that I promised previously.