Here is a quick tutorial to demonstrate how to create a new Quartus II HDL project, compile it, then download it to your device.

Before we start there are a couple of prerequisites you’ll have to take care of first if you wish to follow along.

  • Obviously, you will need to get your hands on a Cyclone II. If you’ve been reading some of my other blog posts you’ll know I’m using this setup. Your results will vary with different setups.
  • Download and install Quartus II FPGA design software here. The Web Edition is $free. (The main drawback is the free edition only works with Windows). Feature Comparison
  • If you’ve never worked with an FPGA, or any HDL language, go start working your way through the Altera training courses. They have an entire curriculum with all the information you’ll need to know to work with the Quartus II software. Once you get about 50% through the The Quartus II Software Design Series: Foundation class (and its “prerequisite” classes), then you’ll understand pretty much everything in this post.
  • (As a heads up, take the Verilog course instead of the VHDL one, since that is what I’ll be using ;-))

Quick disclaimer: the following directions are based on using Quartus II 9.1sp1 software.

Okay, to start off, lets open Quartus II and create the software for our “Hello World” demo. Next, we’ll setup our hardware, and then download the configuration file.

The project we will be creating is the same shown in my previous demo. Essentially we’ll divide down our input clock, which is running at 48MHz, to something like 1Hz. We’ll connect a multimeter to the FPGA’s output and watch it toggle between High (3.3V) and Low (0V). I know it’s not the most exciting project, but sometimes you have to Shave a Yak before you can make something awesome.

Software Setup:

1. Open Quartus II, and create a new project. (File > New Project Wizard...)

2. Enter the path and name information for your project, and click Next:

3. Skip the Add Files [page 2 of 5] step, we’ll create our own files in a few steps.

4. Select the device we are targeting, we are using the EP2C8Q208C8, and click Finish (we’ll also skip the “EDA Tools and Settings” setup page):

5. Now you should have something like the following:

6. Quartus requires there to be some top level file for which your entire project is derived from. I prefer to use a Schematic document as the top level, this serves as a nice block level overview of the project and its contents. Plus I feel it is a lot easier to connect the wires an buses between the blocks and I/O pins.

So create a new Block Diagram/Schematic File. (File > New)

Now you’ll have an open document called Block1.bdf. Were not going to play with this document quite yet, so go ahead and save it to disk. We’ll come back to it in a little while. (File > Save As...). I recommend saving it with the same name as you chose in step 2. This will automatically select it as the top level file for your project.

If you save it with a different name, you will need to assign it as the project’s top level document by clicking the Files tab in the Project Navigator, then right-click on your Schematic file and click Set as Top-Level Entity, like so:

7. Now we need to add some meat and potato to this project, lets write some HDL to divide down the input clock (48MHz) down to something we can actually observe with our eyes (~1Hz).

Create a new Verilog file (File > New... > Verilog HDL File), and save it as SlowClock.v (File > Save As...)

8. Copy and paste the following code into your newly created SlockClock.v file:

//Generate a very slow clock from the 24MHz input clock
module SlowClock(clock_in,clock_out,hi_out);
	//Input Ports
	input clock_in;
	//Output Ports
	output clock_out;
	output hi_out;
	//Port Definitions
	wire clock_out;
	wire hi_out;
	reg [26:0] counter; //Clock Divider
	//Set the output pin to the MSb of the counter.
	assign clock_out = counter[26]; 
	assign hi_out = 1'b1;
	//Essentially the counter counts up to 2^27, 
	//	then clock_out flips polarity	
	always @ (posedge clock_in) begin 
		counter <=  counter + 1;
endmodule // End of Module counter

Now you should have something like this:

9. Okay, now that we created the SlowClock.v code, we will need to generate a Symbol File from the code, so that we can drop it into our top-level Schematic

In the Project Navigator, click the Files tab. Then Right-Click the SlowClock.v file, and click on the Create Symbol Files for Current File. Quartus will churn through the Verilog file for awhile and return a message box indicating success, or a failure if there was an error during symbol creation.

10. Now that the symbol file has been created let’s drop it into the top-level schematic. Re-Open the Hello_World.bdf file. Right-Click anywhere on the schematic and click (Insert > Symbol...). Open the Project folder and highlight the SlowClock item, then click OK. Then in the schematic file, click anywhere to place the SlowClock block:

You should have something like this:

11a. Next we need to place some I/O pins into the schematic. Again right click on the schematic and click (Insert > Symbol...). Navigate to the (primitives > pin) and select and place an input pin:

11b. Repeat step 11 but place an output pin, you should now have something like the following:

12. Next we need to connect the pins to the block. When you put your mouse next to the pin or block, the mouse will change to the node tool.

Connect the input pin to the clock_in, and the output pin to the clock_out.

13. Double click on the “pin_name” and “pin_name1” in order to rename them to something more useful. Try clk, and clk_out:

14. Now that we have the pins placed, we need to assign those pins to actual physical pins on the hardware (on the Cyclone II FPGA). The tool for this is the Pin Planner. But before we use that tool, we need to tell Quartus to analyze the files in order to make our input/output pins we placed available in said Pin Planner tool.

Click on the Start Analysis & Synthesis tool in the toolbar:

Quartus will churn for awhile, then report it’s success or failure.

15. Next, open the Pin Planner tool. (Assignments > Pins...):

16a. For the clk node, double click the Location text box, and assign it to Pin 77:

16b. Next, set the clk_out node to Pin_59:

17. One last step left for the software setup. Close out of the Pin Planner. Now we can do a Full Compile of the project to generate the configuration file. The configuration file is what we download to the FPGA.

Click the Start Compilation button in the toolbar:

Quartus should grind for awhile and eventually give a popup declaring success.

Hardware Setup:

18. Connect the 48MHz clock to Pin 77.

19. Connect your multimeter to Pin 59.

20. Connect your Altera Programmer to the FPGA breakout board’s JTAG port, then connect it to your computers parallel port.

21. Turn the power on. (3.3V VCCIO, 1.2V VCCINT)

Easy as that, now we can download the configuration file and were done.

Programming the Cyclone II:

22. Back in the Quartus II software, run the Programming tool (Tools > Programmer).

23. Make sure you are configured to use the ByteBlaster configuration hardware.

(I ran into some problems with this step. Turns out my Parallel port was disabled in the Bios. Once I enabled the port in the Bios, I had to uninstall and re-install the Parallel port in my Windows Device Manager.

24. Click the Start button to download the configuration file to hardware.

You should now have project running and hopefully it looks like this:

(If it does, feel free to give off an evil-mad scientist laugh at this point. Good work!).

Hopefully that helps you get up and running with the Cyclone II FPGA. Feel free to leave some feedback in the comments section about how this process went for you. Let me know if you run into any problems along the way. Good Luck!!

You can download the Quartus II Project I created for this demo here:

Hello World Quartus II Project
(Hello World Quartus II