In case you’ve stumbled across my blog from EEWeb, I just want to thank you for coming to check out my little corner of the internet. Feel free learn a little About me, peruse the articles I have written and perhaps, if you’re intrigued, you’ll subscribe to my RSS feed and stop by now and then as new posts go up.

I’ll warn you that my idle time has been heavily consumed by some courses I’ve been taking through UC Berkeley Extension. I’ve been working my way through their Integrated Circuit Design and Techniques Certificate program. Therefore, posting frequency has been lighter lately than I would like. All the more reason to subscribe to the RSS feed 😉

I’ve put together a little list of my more popular posts here on Idle-Logic.com:


 

Talking to the DE0-Nano using the Virtual JTAG interface.

Shows a technique to setup a communication path between the PC and DE0-Nano using the existing USB connection. With this TCP/IP bridge you can communicate with the device using practically any programming language.

DE0-Nano to Python via TCL


 

Configuring the Cyclone II FPGA

The title about says it all. For this post, I was using a basic FPGA Breakout board. If you dig a little deeper you can see many posts talking about the how the Cyclone II works, what clock I used, and how I powered the device.


 

Programming an Altera Cyclone II FPGA with a FT232RL USB to UART Bridge

Here I show how to program the FPGA via USB instead of using the Parallel port. I found a way to manually bit bang the configuration file into the FPGA using Python and an FT232RL breakout board.


Using ModelSim with Quartus II and the DE0-Nano

This is a little crash course on how to use ModelSim with Quartus design files. I’m planning a new blog post here in the near future talking a little more about fun ModelSim features, and a little more detail about how to exercise the waveforms.


TCL Macro for Top-Level Schematic to Verilog Conversion (For ModelSim Simulation)

For people who like a schematic top-level design, this post shows code I developed to automatically convert the Quaratus top-level schematic to HDL for simulation. (Since ModelSim doesn’t accept schematic files).


Hope you enjoy, thanks again for dropping by.