Jesse, a professor at the The Hague University of Applied Sciences (Netherlands), has been kind enough to share with us his BDF to VHDL conversion script which can also kick off Modelsim. The script is very well documented, definitely worth taking a look.

Head over here and take a look at the Tutorial and a simple example project with all the files required.

Here is a quick link to the Tutorial


Students at The Hague University Of Applied Sciences get their first glimpse at Digital Design education using only schematic entry using the Quartus II software environment. Schematic entry is done using a full screen WYSIWYG editor and generates Block Design Files (BDF files). This is a proprietary file type and is not supported outside the Quartus II environment.

Simulation is at this stage unknown to them. We try to hide as much as possible as not to distract their attention from the design process.

ModelSim is a full fledged VHDL and Verilog simulator and widely spread amongst digital system designers, but is unable to compile and simulate Quartus’ BDF files.

Quartus provides an option convert BDF files to VHDL files. Converting BDF files to VHDL files is a tedious and error prone operation and has to be done every time the design is updated.

This document describes a set of files as part of a design flow that deals with all of the problems mentioned above. The scripts run both on Windows and Linux operating systems. Both the Subscription Edition and the Web Edition are supported.

*I’ve been working on a few updates to my b2vFixer script which works for Verilog which I will share soon, but I suspect Jesse’s script could be updated to convert to Verilog fairly easily as well.