Reader Paul Green was inspired by one of my blog posts, and has done an amazing job of taking it to the next level. The vj-uart
project allows communication to the DE0-Nano using a virtual com port connection.
This tutorial will explain how to pull the files down from GitHub, and how to start talking to the DE0-Nano using PuTTY. (You can use any of the many available tools that can make a telnet
connection, but my preference is PuTTY.
Getting the DE0-Nano Configuration File
The FPGA project is essentially a Virtual JTAG connection set up in a loop back configuration. In other words any data you send to it should be sent right back, a good way to ensure everything is connected and running properly. Once you’re sure things are working you can extend the vj-uart
to work with your own project.
You can find the vj-uart
project over on GitHub here. If you’re not familiar with GitHub and their Source Control tool, you can just download all the files as a zip file, just look for this button
Once you’ve downloaded the project, open the Quartus Project File: DE0-Comm.qpf
Use the Processing menu, and Compile the project as you normally would:
Once you’ve finished compiling, open the FPGA programmer in the Tools menu:
If the programmer shows that no hardware is connected, like this:Then just click the Hardware Setup… button, and hopefully you can select it:
Now that the USB-Blaster is setup, click the Start button, and wait until the progress hits 100%:
Running the TCL – Quartus_stp.exe Server
Next, you’ll need to head over to the vj-uart\bin
directory, and find the vjuart.tcl
file.
This is the file you will need to run using quartus_stp.exe
, much like we did with the TCL server in my earlier post.
The
quartus_stp.exe
is an application that is normally used with the Altera SignalTap II. It has the API hooks that let us talk directly to the Virtual JTAG using TCL. Vern Muhr has done some impressive reverse engineering and created theopen_sld
project that bypasses thequartus_stp.exe
application.
I recommend you just make a shortcut that will launch this file inside quartus_stp.exe
, so you don’t always have to type out the full path.
Right click the vjuart.tcl
file, and create a new shortcut. You can rename the shortcut, then you’ll need to update the Target path inside the shortcut path:
The exact path depends on which version of Quartus you’re running but should look much like this:
C:\altera\13.0sp1\quartus\bin\quartus_stp.exe -t "C:\Users\Chris\Dropbox\GitHub\vj-uart\bin\vjuart.tcl"
Once the shortcut is created, launch it and you should see something like this:
Connecting with PuTTY
Head over and download PuTTY if you don’t have it already.
Launch PuTTY and setup the connection using the localhost IP: 127.0.0.1 port 2323:
In order to better see the loopback behavior, I recommend clicking on the Terminal category, and setting the Local Echo to Force on
, and the Local line editing to Force Off
Once you click and open the connection, you should be greeted by a test string of the alphabet. You can then type some characters and watch them be sent back to you:
That’s all!
I hope you’ve enjoyed this tutorial. Soon I’ll put together a more practical project, probably a small project that writes characters to a display. Many thanks to Paul Green for his very well written project!
thanks for you project, I try use it with a DE0-Nano with windows 10, I have problems
C:\Windows\System32>”c:\altera\13.1_Web Edition\quartus\bin\quartus_stp.exe” -t c;\Users\Admin\workspace\fpga\vj-uart-master\bin\vjuart.tcl
Info: *******************************************************************
Info: Running Quartus II 32-bit SignalTap II
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation’s design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Mon Jul 06 22:19:55 2020
Info: Command: quartus_stp -t c;\Users\Admin\workspace\fpga\vj-uart-master\bin\vjuart.tcl
Error (23018): Tcl Script File c;\Users\Admin\workspace\fpga\vj-uart-master\bin\vjuart.tcl not found
Error (23031): Evaluation of Tcl script c;\Users\Admin\workspace\fpga\vj-uart-master\bin\vjuart.tcl unsuccessful
Error: Quartus II 32-bit SignalTap II was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 198 megabytes
Error: Processing ended: Mon Jul 06 22:19:57 2020
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Great post Chris! It worked for me
Great write-up – have used it to form the basis of my own tutorial on vJTAG taps in Altera gear here: https://nextstatefail.wordpress.com/2018/11/25/jtag/
Have made an attribution in the source code and the post chain. Thanks for sharing!
Oops! Sorry for the double post. :-/
Great write-up – have used it to form the basis of my own tutorial on vJTAG taps in Altera gear here: https://nextstatefail.wordpress.com/2018/11/25/jtag/
Have made an attribution in the source code and the post chain. Thanks for sharing!
I have tried your project in my Terasic De0 Nano Soc (cyclone v ) board. But I have some problem in the tcl part. When I am following your tutorial regarding the tcl I got this following message and could not successfully implement the project. May you help me to resolve the issue.
Message :
Info: *******************************************************************
Info: Running Quartus II 64-Bit SignalTap II
Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation’s design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Oct 04 17:31:40 2017
Info: Command: quartus_stp “C:\Users\SUMAN KARAN\Desktop\nnn\vj-uart-master\bin\vjuart.tcl”
Error (262016): Can’t find SignalTap II Logic Analyzer top-level entity “C:\Users\SUMAN KARAN\Desktop\nnn\vj-uart-master\bin\vjuart.tcl”
Error: Quartus II 64-Bit SignalTap II was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 306 megabytes
Error: Processing ended: Wed Oct 04 17:31:47 2017
Error: Elapsed time: 00:00:07
Error: Total CPU time (on all processors): 00:00:01
Hi Karan,
Unfortunately, I have not used that Nano SoC. I think part of the problem is that the actual FPGA is one level deeper in the configuration chain on the SoC than it is on the Nano. I know one other visitor was trying to solve this problem but I never heard if they were successful or not. Good luck!
Hi Chris thanks for your outstanding effort. Its working now for my device.
Awesome! Thanks for letting us know you got it working!
Hi, I have the tutorial working fine, just looking to also be able to read from a different register on the device. I have already added the read function to the python and the new inputs to the verilog, but would I need to change the vJTAG module other than adding a new input? Also I assume the tcl script has to be manipulated as well, but I’m not to familiar with those so any help would be greatly appreciated (or if there is anything else I missed as well.) Thanks in advance.
Hi,
I’d like to replace a USB-UART bridge on my DE0-nano with the USB/JTAG connection so I can have a Tx and Rx pin for my existing project. Can this project do that and create a virtual COM port or will that take additional effort?
Thanks!
Hi Dan,
You can check out my previous blog post which gives a little lower level look into how Paul Green implemented this solution. (http://idlelogiclabs.com/2012/04/15/talking-to-the-de0-nano-using-the-virtual-jtag-interface/)
It’s been awhile since I looked into how he implemented his project, and I’m not 100% certain in what you’re trying to do, but I’m thinking you will need to do a little bit of lifting to tie in his vJTAG logic into your USB-UART bridge receiver, but I would wager it should be fairly straight forward.
Anyway, take a look at that other blog posting to get a better idea of how this whole things works and let me know what you think.
Thanks for stopping by,
Chris
Hello 🙂
So im trying to do the following,
I have this VHDL design and i wish to use this kind of communication to change the values of a few variables/signals in the programm. I just dont understand what i should change to do so. I would love any help 🙂
Thanks in advance
Hi Louis, I hope I can help. I would recommend checking out one of my other tutorials on this topic: http://idle-logic.com/2012/04/15/talking-to-the-de0-nano-using-the-virtual-jtag-interface/
This has a much lower level breakdown of how to use the communication pathway. You would have to translate a small block from Verilog to VHDL, but it shouldn’t be too painful. Take a look and let me know.
Best regards,
Chris
Hey Chris,
Thanks For the quick reply :). So if i understand right, to modify this project and make it send data, cause i have to send 4 word of 16 bits and maybe one signal to be able to control ON/OFF from the PC. So what i have to modify here is the vjtag interface right ?. and replace the leds thing by my project. Also do i need to modify the TCL_Server_vJTAG_SimpleTest.tcl too or is it just a standard file for every jtag command.
Thanks i appreciate it a lot.
I know vhdl but not verilog too much too.
Thanks in advance
Because i just had this idea : So i use this programm which sends letters and i just need to somewhere capt the letters and then i do this ascii – decimal converter, which makes it that you type with the keyboard in the console some caracters and they fill the signals value at some point. Idk
Like for example lets say i want to write 199990 to my first signal. What i do is like i type A into the command to say that its for the first signal, then i type 199990 then space to say the transfer is done. Then if i want to fill the second value i type B then the value then space etc… I think i would be able to do a programm pretty easely that transforms the entry into the values and all, with the help of an ASCII table, The thing is where could i get the caracter that i type in the command :).
Thanks in advance
Hi Louis, sorry for the delay in getting back to you.
You wouldn’t need to modify the tcl file of that project. You would just need to convert the verilog files over VHDL and then ask for Quartus to implement the vjTAG as a VHDL instead of verilog.
Once you get that ported over, you shouldn’t have any problems implementing your program idea 🙂
Hi Chris,
I’m trying to connect to the JTag VComm server using a python socket but I keep getting an error.
Connection from 127.0.0.1
error writing “sock600”: software caused connection abort
while executing
}”ative_puts sock600 {JTAG VComm on 127.0.0.1:2323
(“eval” body line 1)
invoked from within
“eval native_puts $args”
(procedure “puts” line 16)
invoked from within
“puts $channel_name “JTAG VComm on $client_address:$service_port\r””
(procedure “conn” line 16)
invoked from within
“conn sock600 127.0.0.1 51719”
Any ideas what might be causing this?
Thanks!
Hey Alex,
Can you try uploading your code to Pastebin.com for me to take a look at?
Thanks,
Chris
Chris,
I managed to get it to connect now but I’m struggling to get it to acknowledge anything I send to the server. When I connect via putty,I have no issues and the stream byte counter increases as I send bytes over but not when I connect via the python socket.
I’ve attached the simple python script I’m using via paste bin – http://pastebin.com/kG4x0uvM
Thanks for getting back so quick!
This tutorial has been fantastic for the project I’m working on!
Alex
Hey Alex,
Sorry for the delay in getting back to you…
I suspect you’re over complicating the data send portion of your Python code.
What happens if you just try:
s.send(‘A’)
Hi Chris – have you tested what the bandwidth is of this connection?
Would it be suitable for transferring data to/from the SDRAM?
Hi nemgreen, I didn’t test the throughput potential, but it’s a fairly slow data transfer. I would only recommend this technique for passing small amounts of data.
Great tutorial(s), and nice script. I’m trying to use the vJTAG for a different purpose, namely writing serial data from the FPGA to a Keithley SMU (no PC involved). I use a USB to serial converter cable. The commands are relatively simple, ASCII-format messages, but I’m running into some problems. First of all, I cannot figure out where to set the serial connection parameters. I’m not even sure the vJTAG can be used as a proper serial port; any thoughts on this? Am I missing something important?
Hi NDN,
Unfortunately the vJTAG is not the feature you would want to use for talking between the FPGA and the Keithley SMU. For this tutorial, I’m sending Serial Commands on the PC, to the PC Application which is then talking to the FPGA.
For your setup, you probably want to use to make a Serial Interface, something like what you could find here:
http://www.fpga4fun.com/SerialInterface1.html
Hope that helps!
Chris
Hi Chris,
Thanks for your quick response! I had a bit of time in between things and ended up just writing a simple FSM-based UART that looks a lot like the serial interface in the link you shared (just in VHDL). That one works in simulation, so hooking it up to a MAX232 should do the trick. Guess I was just too biased in the direction of vJTAG when I read about it. At least it got me back into interfacing VHDL with Verilog, which is something I hadn’t done in a while, so that was useful. Thanks again! 🙂
Hey NDN,
Sounds like you found a great solution, happy to have helped!
No problem at all, have fun!
Best regards,
Chris
Hi Chris,
thank you for sharing your knowledge, please keep on adding fpga stuff here! it’s a pity that fpga doesn’t quite seem to gain traction in hobbyist world… i’d like to be wrong, but scarcity of resources akin to your blog over the internet just kind of proves it for me… we need more stuff like this!
cheers!
Hi fpgated!
Thanks for your positive feedback! I’ve been elbows deep in a software development project for the last 10 months or so. Once that launches I’ll be back into blogging about FPGA projects. I will probably start to mix the FPGA with the Intel Edison in hopes of attracting a wider audience. I agree with you whole hardheartedly, there aren’t nearly enough resource online right now to help give the average hobbyist enough of a boost to get over the steep learning curve that comes with FPGAs. I hope to help rectify that…
In the meantime, I recommend you follow Michael Field on twitter (https://twitter.com/field_hamster), he is always putting out great tutorials, and fun FPGA projects.
niiice, thanks for the heads-up! will check that out, and i’m (and i guess many others are) waiting forward for your new posts. wish you lots of inspiration in your projects 🙂
and yes, edison does seem like the next big thing!
(sorry, messed up with reply, please delete the wrong one 🙂