Mercurial Source Control for Quartus Projects

In order to better manage my development of Quartus HDL projects I decided to start using source control software. This allows me to easily see the changes I've made through the use of diff tools and actually forces me to document the changes I'm making, while giving me the ability to rollback those changes at any time. A lot of the source control tools are designed [...]

July 22nd, 2012|Categories: HDL, Quartus|4 Comments

TCL Macro for Top-Level Schematic to Verilog Conversion (For ModelSim Simulation)

A new version of this script has been created: Updated b2vFixer.tcl for Quartus / Modelsim Quick Summary:I created a handy script (b2vFixer.tcl) that prepares a Quartus project with a Schematic (BDF) top-level entity for use in ModelSim. My personal preference is to use a Schematic for the Top-Level entity of my FPGA projects. I find that by drawing out the top level it becomes self documenting [...]

June 9th, 2012|Categories: ModelSim, Quartus, Tcl|4 Comments

One of Python’s Hidden Secrets – The Lone Underscore

I've been programming with Python for the last 4 years at my day job, and I've only seen this feature shown once in example code. To be honest, this is not something that you would use very often, but personally there are plenty of times where it comes in handy. This feature works in a script file, but you will surely only use it in the [...]

June 2nd, 2012|Categories: Python|Tags: , |0 Comments

Simulating the Virtual JTAG in ModelSim

Here I'm going to demonstrate how to use ModelSim to test out the Virtual JTAG design that I showed in my previous post. If you're new to ModelSim with Quartus II, I recommend you look at a post I made awhile back which serves as a quick crash course: Using ModelSim with Quartus II and the DE0-Nano Quartus IIThe first step is to open the Virtual [...]

May 28th, 2012|Categories: Altera, DE0-Nano, fpga, ModelSim, Quartus, vJTAG|4 Comments

Talking to the DE0-Nano using the Virtual JTAG interface.

How to communicate between a PC and a design running on the DE0-Nano using the Virtual JTAG Megafunction, a Tcl TCP/IP Server running in quartus_stp with virtually any programming language. *07/05/14 - Reader Paul Green has extended this post's idea and built a virtual com port for talking to the DE0-Nano. Check out his very well written vj-uart project on GitHub. Here is my tutorial on [...]

April 15th, 2012|Categories: Altera, DE0-Nano, Python, Tcl, vJTAG|Tags: , , |132 Comments

Using ModelSim with Quartus II and the DE0-Nano

This is a tutorial to walk you through how to use Quartus II and ModelSim software together to create and analyze a simple design (an inverter), then we'll compare the RTL and Gate-Level simulations with the results on a DE0-Nano. This tutorial assumes you have some basic experience working with Quartus II. Going through the examples in the DE0-Nano User manual should be sufficient. For the [...]

December 4th, 2011|Categories: Altera, DE0-Nano, fpga, ModelSim|Tags: , , , , , , |27 Comments