I created a small improvement to my Quartus b2vFixer.tcl script. You can find the original post describing the purpose of this script here. In summary, this script is used to convert a top-level Quartus BDF (Block Design File) to a Verilog file usable in ModelSim.

The only real change in this update is to allow defparams to be converted correctly.

You can find the updated source code over on Github: b2vFixer

Keep your eye on my new GITHUB tracker widget on the right-side bar of idle-logic.com to find this and other projects I’m working on.