This is a tutorial to walk you through how to use Quartus II and ModelSim software together to create and analyze a simple design (an inverter), then we’ll compare the RTL and Gate-Level simulations with the results on a DE0-Nano.
This tutorial assumes you have some basic experience working with Quartus II. Going through the examples in the DE0-Nano User manual should be sufficient.
For the tutorial, I’m using the following versions of the software:
- Quartus II v. 11.0 Build 208
- ModelSim 10.0C (Quartus 11.1) Starter Edition
You can see the versions of my software aren’t the same, this is probably why I have the EDA tool pathing issue described below. I recommend installing both tools at the same time, from the same release.
Note that you will have to install the ModelSim (Altera Version) software separately from Quartus, Altera’s website makes it seem like they come bundled but this is not the case.
First Step – Create the Design
Start by creating a new project in Quartus II. When using the New Project Wizard
, make sure to select the DE0-Nano’s FPGA which is the EP4CE22F17C6
. Also, select the ModelSim-Altera as the simulation tool and select the format as Verilog HDL.
Create the Inverter HDL Code
Now create a new Verilog file, which you can save as SimpleInverter.v.
module SimpleInverter(
input wire a,
output wire a_bar
);
assign a_bar = ~a;
endmodule
Now you need to set the Inverter as the TopLevel Entity
You’ll need to run the Analysis & Synthesis portion of the compilation process to prepare the files for ModelSim
RTL Level Simulation with ModelSim
Now that the HDL has been created we can start ModelSim (from within Quartus) to do the RTL verification and ensure the design works as we expect.
Start ModelSim using the menu: Tools -> Run EDA Simulation Tool -> EDA RTL Simulation
If you get an error message where the path to the ModelSim software is not specified, search your C:\altera folder for the vsim.exe file. Then update the path by using the Tools -> Path
menu, next set the path in the EDA Tool Options
category
It’s quite confusing the first time you use ModelSim from Quartus because after ModelSim opens it doesn’t give you any tips as to where your Inverter went. By default the Inverter is put into the “work” Library.
Once you find the module, double click it, or right click and start the simulation:
Now you should see something like this:
If you don’t see all these windows you can bring them up from the Windows -> Toolbar
menu.
Create a Stimulus
First thing we need to do is to create a stimulus on our input (a
), you can right click the a
in the Objects
window and for this example let’s just make it a clock:
Let’s make it a 20Mhz clock, so a period of 50nS, make sure to keep the lowercase “ns” or ModelSim will complain.
Next, we’ll add the two signals (a
and a_bar
) to the Wave window, there are a few different ways to do this, but I prefer to just shift-select both a
and a_bar
and drag-drop it into the Wave window:
Simulate some Time
Now we need to tell ModelSim to start simulating some portion of time, so lets click the Run button after adjusting the RunLength to 200nS:
Now you should see something like the following in the Wave window:
We need to re-zoom the Wave window to better see the simulation:
You can also change the “Radix” so the values will come up as binary and not “St1” and “St0”, just shift-select both signals, right click and select Radix…
And select “Binary”:
Analyzing the signal
You can zoom in on the signal easily using the CTRL+Mousewheel. Now we can see that our design is working exactly as we expect an ideal inverter to work. There is no propagation delay between a
going high and a_bar
going low:
Simulating a Real-World Inverter (Gate-Level Simulation)
In order to see what a non-ideal inverter might look like, let’s jump back to Quartus.
Assign pins
Open the pin planner and assign the following pins:
Here is the location of the pins we chose:
Full Compilation
Now kick off a full compilation:
Gate Level Simulation
Now that the full compilation has finished, we can run gate level simulation. This will include some of the real-world delays and give us a better expectation of how the design will really work.
Using the Tools
menu, start the gate level simulation:
Next, you’ll be asked which timing model you want to use, let’s just pick the default, “Slow -6 1.2V 85 Model”, this simulates nominal core voltage at 85degC.
If you get a NativeLink error, something like “error deleting "msim_transcript": permission denied.
” you’ll need to make sure you close your current ModelSim environment, or at least stop the current simulation.
Kicking off the Gate-Level Simulation
Now comes a little trick to start this simulation. If you try to begin the gate-level simulation like we did with the RTL simulation (double clicking the work/SimpleInverter
module), you’ll be given the following error:
# Loading work.SimpleInverter # ** Error: (vsim-3033) SimpleInverter_6_1200mv_85c_slow.vo(67): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found. # Region: /SimpleInverter # Searched libraries: # C:\altera\11.0sp1\simulation\modelsim\gate_work # ** Error: (vsim-3033) SimpleInverter_6_1200mv_85c_slow.vo(77): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Region: /SimpleInverter # Searched libraries: # C:\altera\11.0sp1\simulation\modelsim\gate_work # Error loading design
We need to start the simulation and tell it where to find the Cyclone IVe I/O pin library.
We’ll click the Simulate -> Start Simulation...
menu:
In the Design
tab, enter the work.SimpleInverter
as the Design unit:
Next we click the Library
tab, and add the cycloneive_ver
(“ver
” for the verilog version of the Library). (Make sure you have the “e” after the “iv” otherwise your design will fail.)
After you kick off the simulation you’ll be presented with a similar ModelSim simulation as before, however there are now a few extra signals and design units. You can see the signals we care about, a
and a_bar
are still present.
Simulate
Let’s add those signals to the Wave
window, create an input stimulus on the a
signal and start a 200nS simulation like we did in the RTL Simulation above.
Analyzing the Results
Now we see a very different behavior than we saw in the RTL simulation, there is some propagation delay between a
going high and a_bar
going low.
Measuring Propagation Delay
You can add a second cursor to the wave window by clicking the “Insert Cursor
” button:
We can see ModelSim and the Altera models are estimating a 6.7nS delay.
Verifying in Hardware
In order to verify the results given in ModelSim, I downloaded the configuration file to my DE0-Nano. Using a pulse generator and an oscilloscope I was able to collect the following data. (Data was pulled from the scope and regenerated in Python using matplotlib)
Zooming in a little closer, we can measure a propagation delay of about 6.5nS, quite close to the results given in the simulation. (My testing was done at ~30degC not the 85degC)
In this tutorial, we’ve covered the basics of running simulations in ModelSim of designs created in Quartus II. Let me know if this was useful and informative, or if I’ve left anything important out.
Further Reading:
MIT ModelSim Tutorial (Introductory Digital Systems Laboratory)
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[…] more info […]
[…] switching back to the hardware domain and the DE0-Nano. I still have some work to do to improve the ModelSim/Quartus workflow, and create a more robust communication framework between the PC and DE0-Nano via the USB […]
thanks i could solve it
Excellent, glad you got it going. Have fun.
hello
i have a problem with gate level modeling as you mentioned i tried to add cycloneive_ver but i think i cant create it the following errors establish when i want to simulate can u help me thanks
Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(4985): Instantiation of ‘cycloneii_routing_wire’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(5006): Instantiation of ‘cycloneii_io’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(5025): Instantiation of ‘cycloneii_routing_wire’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(5046): Instantiation of ‘cycloneii_io’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(5065): Instantiation of ‘cycloneii_routing_wire’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
# ** Error: (vsim-3033) PPA.vo(5086): Instantiation of ‘cycloneii_io’ failed. The design unit was not found.
#
# Region: /PPA
# Searched libraries:
# C:/altera/72/quartus/DDFS_lateral/PPA/simulation/modelsim/gate_work
[…] Using ModelSim with Quartus II and the DE0-NanoThis is a little crash course on how to use ModelSim with Quartus design files. I’m planning a new blog post here in the near future talking a little more about fun ModelSim features, and a little more detail about how to exercise the waveforms. […]
Hi Chris ,
Thank you for your reply…..
hi chris …..i am also using de0 nano altera kit….and i have decided to use verilog for programming de0 nano fpga…..i am kind a new to this ….do you have some simple information about how to program ang simmulate and also run the same program on deo nano……i have reffered the user manual and also have experimented with the given examples…..i have quartus ii 10.1 web edition and model sim se 6.6 c …..i am trying to make a very good filter on de0 nano…..can you help me with this……
Hi Vaishali,
Is there a particular aspect of the flow you are struggling with? I think the two demo/tutorials that come with the DE0-Nano user manual are very good at explaining the basics of creating a new design, compiling and programming. I feel this blog post covers the portion of taking a design from Quartus into ModelSim and doing a basic simulation.
A good source for Verilog help is this website: http://www.asic-world.com/verilog/veritut.html
I also wrote this tutorial awhile back for another FPGA board, but a lot of the process is the same for the DE0-Nano:
http://idle-logic.com/2010/04/19/configuring-the-cyclone-ii/
Hope that helps!
Hi, I’m a hobbyist and while my circuit seems to work, it looks nothing like the simulation.
In my case I try to talk to the ADC unit.
so, two suggestions for improvement of your excellent tutorial:
– how to create a random wave vector. e.g. I need a reset pulse, just one of about 3 clockticks, occuring at 2000ns. how to enter such a waveform ?
– short pointer on how to go about internal registers that remain a red line ? I fear they might be optimized away or something..
Hi Ronald,
Thanks for the kind words, and great suggestions. When I have some more time I’ll put together a post talking about had to add stimulus to the simulations, both from the Quartus side, and in the Modelsim side.
Hi sds, thanks for the feedback.
To do the Gate Level Simulation, make sure you first do a “Full Compilation” (See that section above), this should run the EDA Netlist writer for you.
To quote one of the Altera manuals: “To perform gate-level timing simulation, EDA simulators require the cell delay and interconnect delay information of the design”, this is what the EDA Netlist Writer provides.
(Make sure your project has ModelSim-Altera setup as the simulation tool before the compile).
Let me know if that solves your problem.
Hi ! It was so useful , Tnx !
I have a problem in gate level simulation . I’m trying to test my adder in gate level simulation, but It said that it cant find the file “test.sft” .(my project name is test) and said that ” run the EDA Netlist Writer . what is that ?
Buon giorno Leonardo! You are right I’ve been slacking in the blogging lately. I just finished up a challenging course and now I have some idle time, I’ll get back to it very soon 🙂
Thanks for motivating me!
Ciao,
Chris
Keep blogging on DE0-Nano, it is very interesting!
Ciao
Hi Chris,
Great introduction, has saved me hours, many thanks. Just one question, I have a design that uses a Megafunction and Modelsim complains that it can’t find it. Any suggestions as to how you can simulate when Megafunctions are included.
Thanks
Hammy
Hey Hammy,
You’re welcome!
I haven’t used any megafunctions with ModelSim yet, so I’m not positive how to get them to work. I’m guessing you’ll need to add the megafunction to the ‘Library’ prior to starting the simulation, similar to how you added the “cycloneive_ver” to the Library…
I’ll take a look when I get a chance, but if you figure it out, please drop by and let us know 🙂
Glad to hear it. I wish the software had better ways to auto-upgrade, or to notify you automatically of updates. Ah well, some day I’m sure.
I just installed QuartusII 11.1sp1 and Modelsim 10.0c starter edition, and the gate-level simulation works perfectly, thanks for the help.
No problem. Let me know if you still run into problems after the upgrade.
Hii im facing the problem of getting the delay in gate level simulation. Infact the simulation is same as rtl level simulation without any delay.
Hii im facing the problem of getting the delay in gate level simulation. Infact the simulation is same as rtl level simulation without any delay…
Hi Chris, you are right, Im using Quartus II 10.1 and ModelSim 6.6c, that must be the problem. I’m going to update de version and see what happen, thanks for the info.
Hi Rodrigo,
Hopefully I can help. What versions of Quartus and ModelSim are you using? It looks like this might be a problem with the Software version 10.1, but is fixed with the 10.1sp1 software.
Sounds like an upgrade might get you all fixed up.
Let me know.
Hello. thank you for the example, it has been very useful for me. but I have a problem when I try to simulate at Gate-Level. this error appears in my transcript chart:
# Loading instances from SimpleInverter_6_1200mv_85c_v_slow.sdo
# ** Fatal: SDF files require Altera primitive library
# Time: 0 ps Iteration: 0 Instance: /SimpleInverter File: SimpleInverter_6_1200mv_85c_slow.vo
# FATAL ERROR while loading design
# Error loading design
Please, can you help me with this. thanks